The three-dimensional (3D) integration of two or more semiconductor structures can produce a number of benefits to microelectronic applications. For example, 3D integration of microelectronic components can result in improved electrical performance and power consumption while reducing the area of the device foot print. See, for example, P. Garrou, et al., “The Handbook of 3D Integration,” Wiley-VCH (2008).
The 3D integration of semiconductor structures may take place by the attachment of a semiconductor die to one or more additional semiconductor dies (i.e., die-to-die (D2D)), a semiconductor die to one or more semiconductor wafers (i.e., die-to-wafer (D2W)), as well as a semiconductor wafer to one or more additional semiconductor wafers (i.e., wafer-to-wafer (W2W)), or a combination thereof.
The bonding techniques used in bonding one semiconductor structure to another semiconductor structure may be categorized in different ways, one being whether a layer of intermediate material is provided between the two semiconductor structures to bond them together, and the second being whether the bonding interface allows electrons (i.e., electrical current) to pass through the interface. So called “direct bonding methods” are methods in which a direct solid-to-solid chemical bond is established between two semiconductor structures to bond them together without using an intermediate bonding material between the two semiconductor structures to bond them together. Direct metal-to-metal bonding methods have been developed for bonding metal material at a surface of a first semiconductor structure to metal material at a surface of a second semiconductor structure.
Direct metal-to-metal bonding methods may also be categorized by the temperature range in which each is carried out. For example, some direct metal-to-metal bonding methods are carried out at relatively high temperatures resulting in at least partial melting of the metal material at the bonding interface. Such direct bonding processes may be undesirable for use in bonding processed semiconductor structures that include one or more device structures, as the relatively high temperatures may adversely affect the earlier formed device structures.
“Thermo-compression bonding” methods are direct bonding methods in which pressure is applied between the bonding surfaces at elevated temperatures between two hundred degrees Celsius (200° C.) and about five hundred degrees Celsius (500° C.), and often between about three hundred degrees Celsius (300° C.) and about four hundred degrees Celsius (400° C.).
Additional direct bonding methods have been developed that may be carried out at temperatures of two hundred degrees Celsius (200° C.) or less. Such direct bonding processes carried out at temperatures of two hundred degrees Celsius (200° C.) or less are referred to herein as “ultra-low temperature” direct bonding methods. Ultra-low temperature direct bonding methods may be carried out by careful removal of surface impurities and surface compounds (e.g., native oxides), and by increasing the area of intimate contact between the two surfaces at the atomic scale. The area of intimate contact between the two surfaces is generally accomplished by polishing the bonding surfaces to reduce the surface roughness up to values close to the atomic scale, by applying pressure between the bonding surfaces resulting in plastic deformation, or by both polishing the bonding surfaces and applying pressure to attain such plastic deformation.
Some ultra-low temperature direct bonding methods may be carried out without applying pressure between the bonding surfaces at the bonding interface, although pressure may be applied between the bonding surfaces at the bonding interface in other ultra-low temperature direct bonding methods in order to achieve a suitable bond strength at the bonding interface. Ultra-low temperature direct bonding methods in which pressure is applied between the bonding surfaces are often referred to in the art as “surface assisted bonding” or “SAB” methods. Thus, as used herein, the terms “surface assisted bonding” and “SAB” mean and include any direct bonding process in which a first material is directly bonded to a second material by abutting the first material against the second material and applying pressure between the bonding surfaces at the bonding interface at a temperature of two hundred degrees Celsius (200° C.) or less.
Direct metal-to-metal bonds between active conductive features in semiconductor structures may, in some instances, be prone to mechanical failure or electrical failure after a period of time even though an acceptable direct metal-to-metal bond may be initially established between the conductive features of the semiconductor structures. Although not fully understood, it is believed that such failure may be at least partially caused by one or more of three related mechanisms. The three related mechanisms are strain localization, which may be promoted by large grains, deformation-associated grain growth, and mass transport at the bonding interface. Such mass transport at the bonding interface may be at least partially due to electromigration, phase segregation, etc.
Electromigration is the migration of metal atoms in a conductive material due to an electrical current. Various methods for improving the electromigration lifetime of interconnects have been discussed in the art. For example, methods for improving the electromagnetic lifetime of copper interconnects are discussed in J. Gambino et al., “Copper Interconnect Technology for the 32 nm Node and Beyond,” IEEE 2009 Custom Integrated Circuits Conference (CICC), pages 141-148.
FIGS. 1A and 1B illustrate a problem that may be encountered in direct bonding methods. Referring to FIG. 1A, a semiconductor structure 10 is illustrated that includes a device layer 12, which may comprise a plurality of device structures, although such structures are not illustrated in the simplified figures. Dielectric material 14 is disposed over the device layer 12, and a plurality of recesses 16 extend into the dielectric material 14 at locations at which it is desired to form conductive elements such as conductive pads, traces, vias, etc. Thus, electrically conductive metal 18 (e.g., copper or a copper alloy) has been deposited over the dielectric material 14 such that the conductive metal 18 fills the recesses 16. Excess conductive metal 18 is often deposited, such that a layer of the conductive metal 18 extends over the major upper surface 15 of the dielectric material 14, as shown in FIG. 1A.
After depositing the conductive metal 18 to form a semiconductor structure 10 as shown in FIG. 1A, the excess conductive metal 18 is removed from the major upper surface 15 of the dielectric material 14 to form a semiconductor structure 20 as shown in FIG. 1B. Removal of the excess conductive metal 18 defines device structures 22 that comprise the conductive metal 18 in the recesses 16. For example, a chemical-mechanical polishing (CMP) process may be used to remove the excess conductive metal 18 from the major upper surface 15 of the dielectric material 14 and define the device structures 22. The CMP process used to remove the excess conductive metal 18 from the major upper surface 15 of the dielectric material 14, however, may result in the exposed surfaces 23 of the device structures 22 being recessed relative to the surrounding major upper surface 15 of the dielectric material 14. The exposed surfaces 23 may have an arcuate, concave shape as shown in FIG. 1B. This phenomenon is often referred to in the art as “dishing.” Also, the CMP process used to remove the excess conductive metal 18 from the major upper surface 15 of the dielectric material 14 also may cause excessive removal of the dielectric material 14 at certain locations, such as the locations 26 between closely separated device structures 22, as well as random locations on the major upper surface 15 of the dielectric material 14, such as the location 28 shown in FIG. 1B. Such excessive removal of the dielectric material 14 below the primary plane of the major upper surface 15 of the dielectric material 14 is often referred to in the art as “erosion.” These dishing and erosion phenomena may result from non-uniformity of the CMP process, and/or non-uniformity in the initial thickness of the layer of conductive metal 18 over the major upper surface 15 of the dielectric material 14.
Dishing of the exposed surfaces 23 of the device structures 22 and localized erosion of the major upper surface 15 of the dielectric material 14 may adversely affect the strength of a bond and electrical connection subsequently established between the semiconductor structure 20 of FIG. 1B and another semiconductor structure (not shown) in a direct bonding process.